1. Field of the Invention
The present invention relates generally to an integrated circuit which is provided with an improved method and hardware arrangement for substituting a redundant function block(s) for a defective one(s) during fabrication of the circuit. The block replacement is effectively implemented using improved block connection techniques.
2. Description of Related Art
It is a common practice to design an integrated circuit (IC) with redundant circuitry in order to enhance the yield of chips. The present invention is concerned with an integrated circuit which includes two function block groups. Each of these groups is composed of a plurality of function blocks with reiterative circuitry. The function blocks of one group are coupled to the function blocks of the other group on a one to one basis.
Before turning to the present invention it is deemed preferable to briefly discuss a conventional defective block replacement with reference to FIG. 1.
The arrangement of FIG. 1 includes first and second function block groups 10 and 12. The function blocks of the first group 10 are to be coupled to the function blocks of the second group 12 on a one to one basis via a switchable block connector 14.
It is assumed that the first function block group 10 is composed of a plurality processor blocks P1-P16, while the second function block group 12 is composed of a plurality of memory blocks M1-M20 which includes four redundant blocks in this case.
As is known, a memory block is composed of a plurality of memory cells each of which has extremely fine structure. Thus, the memory block is inevitably liable to induce defect as compared with the processor block. For this reason, the memory block group is provided with a plurality of redundant blocks.
Merely for the sake of discussion, it is assumed that there is no defective block in the processor block group,
As shown, the switchable block connector 14 is configured such that each of the processor blocks P1-P16 is coupled to one of the two memory blocks. In the case shown in FIG. 1, two memory blocks M13 and M14 are not coupled to the switchable block connector 14.
The prior art has not given any suggestion that each processor block is coupled to more than two memory blocks. Thus, if a chip includes two adjacent defective memory blocks, there is no means for saving the chip.